Partcl is developing the next generation of chip design automation tools.

Using GPUs and AI, we are developing design tools that are 1000x faster than legacy options. That’s the difference between waiting weeks vs. minutes for design feedback.

Talk to us if you want to build the foundation of artificial intelligence.

Partcl is the vibe coding platform for chip designers.

I was told to make this job description “sound cool and not corporate” so I had ChatGPT translate it into gen alpha:

EDIT: We had an overwhelming number of applicants, so we’re having everyone do a short take home challenge and we’ll interview the people who do well on this: https://github.com/partcleda/intern_challenge

About Partcl

We’re cooking the next wave of chip‑design automation—built for speed, scale, and builder productivity. We believe AI should level up hardware engineering, and the first W is smarter optimization tools.

If you want to tackle massive‑scale problems in physical AI, Partcl is the move.

What you will do:

• Cook + train custom models to go after NP‑complete optimization problems (smart heuristics that actually ship, fr)
• Spin high‑perf CUDA kernels for training + inference and make them zoom
• Speedrun parsers that chew through massive files without choking
• Build ultra‑lean, cache‑friendly data structures — minimal mem, max throughput
• Hook up an LLM interface to those structures so users can literally talk to their design

What you bring:

• Python + PyTorch skills from classes or projects; you’ve trained & evaluated custom models (not just “wrapped a GPT,” fr)
• Systems intuition: you grok memory hierarchies, latency vs. throughput trade‑offs, & why cache misses make everyone sad
• Some CUDA exposure or you’re dangerously motivated to pick it up fast—kernels don’t scare you
• Range: you can bounce between model design, low‑level perf work, and scalable system plumbing (think N → 10M+)
• Tooling chops: you’ve at least dabbled in GPU profiling/perf analysis and you’re down to go deeper

Bonus XP (nice to have)

• Any exposure to EDA / chip design flows
• Reinforcement Learning beyond toy notebooks
• Research or serious projects in compilers / programming languages / databases
• Publications in respected venues (conference/journal/tech reports)
• Physics‑driven ML or numerics that make simulators blush

Why this rocks

• Work on problems where milliseconds matter and terabytes aren’t “big,” they’re Tuesday.
• Ship code that touches real silicon workflows.
• Learn from builders who live at the ML × systems × hardware edge.

Pull up with your resume/portfolio/GitHub. Let’s build.